1. Field of the Invention
The present invention relates to a microprocessor having an error, interrupt, and trap processing function for handling reset, exception, interrupt, and trap processes occurring during program execution, and relates further to an error, interrupt, and trap processing method.
2. Description of Related Art
When a microprocessor is initialized or reset, an initialization program stored in an internal or external memory is run to initialize internal chip states. After running the initialization program, the microprocessor runs a user application program stored in an external memory.
Exception, interrupt, and trap processes (referred to below as EIT processes) are typical of processes that interrupt and change the execution sequence of a user application. An exception process is performed, for example, when an instruction code other than one of the reserved instruction codes is decoded, or when the program attempts to access an memory area that is prohibited to access. Interrupt processes include the above-noted reset process, interrupts asserted from an external device, and interrupts used for debugging. Trap processes test particular conditions so that a corresponding routine can be executed, such as an EIT process executed by an instruction in the program, and include normal error traps and debugging traps.
One method for performing an EIT process is to branch the program sequence directly to a fixed EIT vector area stored in an external memory. The EIT vector area is normally located at a fixed address in the external memory, and the application program developer cannot change the storage address of the EIT vector area.
The operating speed of external memory is also typically lower than the internal operating speed of the microprocessor, and accessing an EIT vector area in the external memory for every EIT process is a factor lowering the processing capacity (throughput) of the microprocessor.
Japanese Unexamined Patent Laid-Open Publications SHO62-282335, HEI1-219930, HEI6-124212, HEI6-324884, and HEI7-262023 teach various methods for increasing the degree of freedom of program design and increasing the speed of EIT processes. These methods typically enable the EIT vector area storage address to be changed by copying the EIT process program to the microprocessors internal RAM and using registers to store the addresses to which an EIT process branches the program sequence. EIT process speed can thus be improved by designing all EIT processes other than reset processes to branch the control sequence to address internal RAM.
Japanese Unexamined Patent Laid-Open Publications SHO62-282335 and HEI5-27989 also teach various microprocessors for achieving high speed EIT processing by reserving two EIT vector areas in a memory and switching between these two EIT vector areas when, for example, a same EIT process occurs repeatedly and consecutively.
While not directly related to accelerating microprocessor processing capacity, debugging is an EIT process that is essential to software program development. Japanese Unexamined Patent Laid-Open Publication HEI6-103115 teaches a debugging method for effectively accomplishing this debugging process by starting a pseudointerrupt process without starting a debugging program using a dedicated debugging data table.
As noted above, EIT processes include processes related to the debugging operations required during program development. Therefore, if all branch addresses used by the EIT process can be freely moved as with the above-noted conventional microprocessor, EIT vector addresses for debugging-related EIT processes that should not be changed by the user could be changed. In this case, the program development environment could be crashed.
It is therefore an object of the present invention to provide a microprocessor for achieving high speed EIT processes while also appropriately protecting the user programming environment.
To achieve the above object, a microprocessor according to a first aspect of the present invention has an exception, interrupt, and trap (EIT) processing function for branching a program processing sequence to an EIT vector area and executing an EIT process program when an EIT process is initiated. This microprocessor is connected to an external memory having an EIT vector area containing data for various EIT process programs, including an EIT process program related to program development. Further specifically, this microprocessor comprises an internal memory for storing data identical to the data in the EIT vector area of the external memory; a first determining circuit for determining whether an EIT process initiated during process sequence execution is an EIT process required for program development; and a branch destination changing circuit for setting a process sequence branch destination to the EIT vector area stored in the external memory when the first determining circuit determines the initiated EIT process to be the EIT process required for program development, and setting the process sequence branch destination to the EIT vector area stored in the internal memory when the first determining circuit determines the initiated EIT process to not be the EIT process required for program development.
A microprocessor thus comprised can prevent a user from inadvertently crashing the program development environment by fixing sequence branch destination addresses to the external memory when an EIT process required for program development is executed. Fast EIT processing can also be achieved when the EIT process required for program development is executed by setting sequence branch destination addresses to the internal memory.
Preferably, the EIT process program required for program development and stored to the EIT vector area in the external memory may include debugging related EIT process program data.
According to another aspect of the present invention, there is provided a microprocessor.
Also preferably, where the EIT vector of the external memory includes a reset process program, the determining determines the initiated EIT process is a reset process the branch destination changer setting the process sequence branch destination to the EIT vector area stored in the external memory.
According to another aspect of the present invention, there is provided a microprocessor having an exception, interrupt, and trap (EIT) processing function for branching a program processing sequence to an EIT vector area for executing an EIT process program when an EIT process is initiated. The microprocessor is connected to an external memory having an EIT vector area containing programs for a plurality of EIT processes and comprises an internal memory for storing first data in a first area of the internal memory and second data in a second area of the internal memory, said first data being identical to data in a first portion of the EIT vector area of the external memory while said second data is identical to data in a second portion of the EIT vector area of the external memory.
This microprocessor also comprises a determining circuit for determining whether an EIT process initiated during process sequence execution is a first EIT process, a second EIT process or a third EIT process among the plurality of EIT processes, and a branch designation changer. The branch designation changer sets a process sequence branch designation to the EIT vector area stored in the external memory when the determining circuit determines the initiated EIT process to be the first EIT process; the process sequence branch designation to the first area of the internal memory when the determining circuit determines the initiated EIT process to be the second EIT process; and the process sequence branch designation to the second area of the internal memory when the determining circuit determines the initiated EIT process to be the third EIT process.
The microprocessor thus comprised fixes branch sequence addresses to the external memory during reset process execution, changes the branch address to a first EIT vector area copied to the internal memory when an EIT process required for program development is executed, and changes the branch address to a second EIT vector area copied to the internal memory when an EIT process other than a reset process or an EIT process required for program development is executed.
It is to be noted that EIT process programs required for program development and stored to the EIT vector area in the external memory may include data for debugging related EIT processes, and such debugging related EIT processes are handled as EIT processes for program development. By fixing sequence branch addresses to the external memory when reset processes and debugging related EIT processes are executed, inadvertent crashing of the program development environment by a user can be effectively prevented. High speed EIT process execution can also be achieved when EIT processes other than reset processes and debugging related EIT processes are executed by changing sequence branch addresses to the internal memory.
The present invention furthermore provides an exception, interrupt, and trap (EIT) processing method used by a microprocessor for branching a program processing sequence to an EIT vector area for executing an EIT process program when an EIT process is initiated. This microprocessor is connected to an external memory having an EIT vector area containing data for various EIT process programs, including an EIT process program related to program development. This EIT processing method more specifically comprises storing data identical to the data in the EIT vector area of the external memory to the internal memory of the microprocessor; determining whether an EIT process initiated during process sequence execution is an EIT process required for program development; and setting the process sequence branch designation to the EIT vector area stored in the external memory when determined the initiated EIT process to be the EIT process required for program development. This setting step sets the process sequence branch destination to the EIT vector area stored in external memory when determined the initiated EIT process to not be the EIT process required for program development.
An EIT processing method thus comprised can prevent a user from inadvertently crashing the program development environment by fixing sequence branch destination addresses to the external memory when the EIT process required for program development is executed. Fast EIT processing can also be achieved when an EIT process other than the EIT process required for program development is executed by setting sequence branch destination addresses to internal memory.
The present invention also provides an exception, interruption, and trap (EIT) processing method used by a microprocessor with an internal memory for branching a program processing sequence to an EIT vector area for executing an EIT process program when an EIT process is initiated. This microprocessor is connected to an external memory having an EIT vector area containing programs for a plurality of EIT processes. This method comprises storing data identical to data in a first portion of the EIT vector area of the external memory in a first area of the internal memory and second data identical to data in a second portion of the EIT vector area of the external memory; determining whether an EIT process initiated during process sequence execution is a first EIT process, second EIT process or third EIT process among the plurality of EIT processes; and setting a process sequence branch designation to the EIT vector area of the external memory when the initiated EIT process is the first EIT process, to the first area of the internal memory when the initiated EIT process is the second EIT process, and, to the second area of the internal memory when the initiated EIT process is the third EIT process.